Integrated circuit semiconductor chips are in widespread use in a great variety of both commercial grade and high-reliability applications. As the manufacturing technology progresses, more and more circuit elements can be placed on a single chip. These chips must be incorporated into a system by mounting them, ordinarily on a printed circuit board, to interconnect with the rest of the elements of the system, many of which are also semiconductor chips. Semiconductor chips are readily available in packageable form from semiconductor manufacturers, and are customarily packaged in any of a number of different enclosures to allow convenient interconnection onto the printed circuit boards, including dual in-line packages (DIPs), J-mounts, and surface mount packages, among others. To decrease the size of the overall system, it is desirable to make the printed circuit board as small as practicable, but this decreases the space available for mounting packaged chips. One solution to this dilemma is to stack chips vertically so that multiple chips can be attached to the system using the footprint area of a single chip.
Stacking of chips into multi-chip modules (MCMs) is especially advantageous in the case of memory chips, since a plurality of identical chips can be used to multiply the amount of memory available, but the principle is also applicable to other digital and analog circuits. MCMs generally contain many silicon chips densely packaged together in a metal or ceramic package that can be hermetically sealed. When constructing MCMs that are expected to perform over an extended temperature range, for example -55.degree. C. to +125.degree. C., it becomes important to have high confidence that each die will perform as expected. If a particular chip fails in an MCM the chip must be identified and replaced, and the entire test sequence repeated on the MCM. This is time consuming, costly, and may affect reliability. Some semi-conductor manufacturers are in the process of establishing "known good die" for use in such applications. These known good die are typically installed in sophisticated fixtures that make electrical contact with each pad on the silicon chip. The chip is then put in burn-in at elevated temperature to weed out the infant mortalities. Chips that pass this test may then be sold as "known good die." This type of test still does not guarantee that the silicon chips will meet their electrical specifications at temperature extremes, and it is therefore desirable to have a structure that permits testing at extended temperatures.
A number of approaches to packaging stacked memory chips or other circuits into modules have been developed, as generally described in "3-D Multichip Packaging for Memory Modules" by R. T. Crowley and E. J. Verdaman, as published in the Proceedings of the 1994 International Conference on Multichip Modules (sponsored by ISHM--The Microelectronics Society and The International Electronics Packaging Society). For example, in U.S. Pat. No. 4,884,237, a standard DIP packaged memory chip is "piggy-backed" onto another such chip, with the corresponding package pins in direct contact and the chip enable pins isolated by rerouting the chip enable of the upper package through an unused pin on the lower package. In U.S. Pat. No. 5,222,014, semiconductor dice are bonded to the upper surfaces of carriers and electronically coupled to the bottoms of the carriers by multi-layered connections or solder-filled through-hole vias; the combinations are then stacked with electrical interconnection between layers accomplished through solder bumps precisely aligned between the top terminal of the lower carrier and the bottom terminal of the upper carrier.
In U.S. Pat. No. 5,128,831, a semiconductor die is face bonded to a carrier substrate containing a metalization pattern that individually connects each chip bonding pad with a package interconnection pad and a substrate via on the periphery of the substrate; frame-like peripheral spacers containing holes that line up with the substrate vias are placed between pairs of die/substrate assemblies, and electrical interconnection between layers is accomplished by vacuum-assisted flowing of solder through the tubes made up of the substrate vias and the corresponding holes in the spacers. In U.S. Pat. No. 4,956,694, memory dice are bonded into the cavities of box-shaped leadless chip carriers and attached to wiring pads that are electrically connected through the carrier walls to conductive channels on the peripheral walls of the carriers; the enclosed modules are stacked and a solder interconnection between the layers is deposited on the assembly.
While all of the foregoing approaches, as well as other approaches, to multi-chip stacking are workable, each has significant disadvantages from the viewpoint of a manufacturer in the business of packaging semiconductor chips generally. The precision alignment needed for face bonding and the process controls needed for proper formation of solder bumps or vacuum flowing of solder through connection tunnels require expensive and specialized equipment.
Thus, it is one object of this invention to provide a module containing a plurality of similar dice stacked into a high density package with a small footprint.
It is another object of this invention to provide a stacked die carrier structure and method of constructing the same that employs standard bonding techniques available to chip packagers.
It is yet another object of this invention to provide a modular stacked die carrier so that individual die modules may be tested before incorporation into the overall assembly, then may be tested again when incorporated into the assembly.